发明名称 FREQUENCY MULTIPLIER CIRCUIT
摘要 PURPOSE:To uniform the duty of an output pulse by connecting delay circuits having an inverting function in cascade connection of plural odd stages. CONSTITUTION:A delay circuit 11 consists of a buffer 8 controlling the charge/ discharge of an integration device 9 and a buffer 10 waveform-shaping the output of the integration device 9 and inverting the waveform. A delay circuit 15 consists of the same constitution as the circuit 11. An output signal 2B delayed by a time t1 from the leading of the input signal 2A and by a time t2 from the trailing is obtained from the delay circuit 11. The signal 2B passed through a delay circuit 15 and retarded by the time t2 from the trailing and by he time t1 from the leading and becomes an output signal 2C. The signal 2C is inputted to a multiplier 16 as a signal delayed by a time (t1+t2) both from the leading and the trailing of the input signal 2A and multiplied with the input signal 2A. Thus, even when the delay time of the delay circuits has variance, a pulse signal having a uniform duty is obtained.
申请公布号 JPS62131624(A) 申请公布日期 1987.06.13
申请号 JP19850271786 申请日期 1985.12.02
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 YANO NOBUMITSU
分类号 H03K5/00 主分类号 H03K5/00
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