发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To speed up working speed by constituting the threshold voltage of a field-effect transistor organizing a memory cell at a value lower than that of a field-effect transistor forming a logic circuit for a peripheral circuit except the memory cell. CONSTITUTION:An MISFET Qm is constructed of a well region 2A having low impurity concentration, and an MISFET Qn is composed of a well region 2B having high impurity concentration, thus constituting the threshold voltage of the MISFET Qm at a value lower than the threshold voltage of the MISFET Qn. That is, the MISFET Qm increases the transfer conductance of a channel forming region (the well region 2A), and current drive capacitance is improved. The MISFET Qm is organized of the well region 2A having low impurity concentration, thus reducing P-N junction capacitance among a source region or a drain region 7 and the well region 2A. Accordingly, the working speed of reading of the informations of a mask ROM can be speeded up.
申请公布号 JPS62224069(A) 申请公布日期 1987.10.02
申请号 JP19860065742 申请日期 1986.03.26
申请人 HITACHI LTD 发明人 MORIUCHI HISAHIRO;SHIBATA TAKASHI;KOBAYASHI ISAMU
分类号 G11C11/407;G11C11/408;H01L21/8234;H01L21/8246;H01L27/088;H01L27/10;H01L27/112 主分类号 G11C11/407
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