| 摘要 |
PURPOSE:To attain the calculation and processing of an executing address at a time by dividing a single instruction for plural operands into plural instructions of a single operand and executing these instructions via a pipeline. CONSTITUTION:The instruction containing plural operands is supplied to a decoding part 1 via a bus control part 7 and converted into an internal instruction. For instance, a push instruction is divided into a load instruction and a store instruction. Then the load instruction is first supplied to an executing part 5 and set to a stage Q1 of a pipeline for calculation of an executing address. Then the load instruction is shifted to a stage Q2 and executed. At the same time, the store instruction is set at the stage Q1 and an effective address is read out. In such a way, the execution of the load instruction and the calculation of the effective address of the store instruction are performed at a time.
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