发明名称 |
Dual fault-masking redundancy logic circuits |
摘要 |
An error correcting logic circuit for masking faults on dual redundant interconnections. Both interconnections are inmput to a NAND or AND circuit which includes pull-up resistors to a high potential. The outputs of all the NAND circuits are connected to dual redundant logic circuits, each of which has an emitter-follower output with a load resistor to ground. The outputs of the redundant logic circuits provide the redundant interconnections to other similar error correcting logic circuits.
|
申请公布号 |
US4719629(A) |
申请公布日期 |
1988.01.12 |
申请号 |
US19850792097 |
申请日期 |
1985.10.28 |
申请人 |
INTERNATIONAL BUSINESS MACHINES |
发明人 |
WANG, WEN-YUAN |
分类号 |
G06F11/18;H03K19/003;H03K19/086;H03K19/173;(IPC1-7):G06F11/18 |
主分类号 |
G06F11/18 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|