| 摘要 |
PURPOSE:To obtain an integrated circuit device which facilitates a scan test including circuit blocks having asynchronous order circuits internally by providing scan registers and gate circuits connected to the scan registers among circuit blocks to be tested and at their connection parts. CONSTITUTION:The scan registers 8a-16a are provided between a combinational circuit block 35 to be tested and asynchronous circuit blocks 36 and 37 including order circuits and at their connection parts. Further, AND gates 70 and 72, and OR gates 71, 73, and 74 are connected to the scan registers 8a-15a. The application of test data to the circuit blocks 35-37 to be tested is enabled at a prescribed fixed value in scan mode and at desired timing in test operation by the gate circuits interposed at the outputs of the scan registers 8a-16a regardless of the outputs of other circuit blocks, thereby preventing data supplied to the circuit blocks to be tested from being varied. |
