| 摘要 |
<p>PURPOSE:To clearly demonstrate the validity or invalidity of tag memory data, to prevent an error due to random data and to speed up initialization by adding a V(validity) bit to data in a tag memory. CONSTITUTION:The V bit is added to a data Au in the tag memory 12, and it is assumed that data is valid and invalid according as '1' or '0' of the bit. Data in the memory 12 is read at an address Ad, and a read-out data RD is inputted to a comparator 14. It compares inputs RD and CD. If they are the same, a coincidence output S1 outputted to a NAND gate G. When the data in the memory 12 is read out at the address Ad, the V bit in a V bit part 12a is also read out, and an output S2 is inputted to the gate G. Even if the S1 is at a level H(coincidence output), the S2 comes to a level L with the V bit set to zero. Accordingly an output S3 is not outputted from the gate G, and 'OK' of reading data memory is not specified. Thus an error caused by random data is prevented, and initialization can be sped up by simultaneously clearing the V bits.</p> |
