发明名称 SYNCHRONOUS DETECTION CIRCUIT
摘要 PURPOSE:To demodulate a reception signal of arbitrary modulation system, by constituting a phase discriminating part of a memory, and connecting an A/D converter to the input part of the memory, and a D/A converter to the output part. CONSTITUTION:A modulation component eliminating part between low-pass filters 5 and 6, and a loop filter 8, is constituted of the memory 10, A/D converters 11 and 12 which convert the outputs of the LPFs 5 and 6 to digital signals, and input them to the memory 10, and the D/A converter 13 which converts the digital output of the memory 10 to an analog signal. The titled circuit is constituted so that a phase deciding data is written in the memory 10 in advance, and addressing is performed by the phase information of the signals from the LPFs 5 and 6, then the lead and lag of the phase is performed, and the degree of the lead and the lag is decided and outputted, thereby, a voltage controlled oscillator(VCO)2 is controlled. In this way, it is possible to easily correspond only by changing the data written in the memory 10, even when an input signal is the one modulated by a four-phase phase shift keying(PSK) system, or an eight-phase PSK system.
申请公布号 JPS6351706(A) 申请公布日期 1988.03.04
申请号 JP19860193921 申请日期 1986.08.21
申请人 FUJITSU GENERAL LTD 发明人 OKADA KAZUO
分类号 H03D3/02;G01S5/14;H03L7/06 主分类号 H03D3/02
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