| 摘要 |
PURPOSE:To simplify the titled circuit by providing nP2-set of pulse number comparison and discriminating circuits setting the initial value, nP2-set of storage circuits outputting two discriminating signals whose logic levels differ from each other, a pulse number maximum/minimum detection circuit and an n-phase clock selection circuit and using an up-down counter to count two input data strings. CONSTITUTION:The pulse number comparison/discriminating circuits 21, 22 are formed by the up-down counter 1 having two inputs. Then the up-down counter 2 is reset at the point of time when two output terminals, a carry terminal CA and a borrow terminal BO, are counted respectively 0 15 and 15 0. The loading value to the counter 2 at the said resetting is selected to be 8 for a binary counter and to be 5 for a BCD counter. The pulse number comparison/discriminating circuit is constituted by one of the up-down counter having two inputs in this way, thereby simplifying the constitution of the n-phase clock selection circuit and reducing the cost. |
