| 摘要 |
PURPOSE:To attain large scale circuit integration with small size by connecting plural identical arithmetic circuits each comprising a multiplier on the Galois field, an adder, and m-stage of register arrays storing its addition output and selector output and using polynomials A, B to obtain its greatest common divisor polynomial GCD [A, B]. CONSTITUTION:In obtaining polynomials A, B and L, M, two independent Process sections are to be provided or one Process section is to be used twice. In using one Process section twice, the processing speed is halved and in providing two Process sections independently, number of required PEs is doubled. For example, the relation of selector selection signals S1, 2=11 is selected only at the input of syndrome polynomials Sx, x<21>, selectors outputting D, E inputs at the X, Y outputs are used. Moreover, in processing A, B and L, M by one processing section, the processing element PE shown in figure is used to control S1-S4 thereby inputting A=x<21>, B=Sx, L=0, M=1.
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