发明名称 PROGRAMMABLE ARRAY LOGIC
摘要 PURPOSE:To decrease the propagation delay time and the program time by providing an AND array while being set into plural number and providing a switch circuit having a function coupling AND arrays and a function leading a prescribed input signal to a selected AND array so as to reduce the chip size. CONSTITUTION:An address data Add fed to an address line 25 is fed to an input line selection decoder 29 and a product term line selection decoder 23 via a switch circuit 24. Cross points of input lines of AND arrays 181-183 and matrixes formed by product term lines are selected based on the output of decoders 29, 23. In giving an input data to product term line drive circuits 191-193 via a switch circuit 27, the connection/non-connection of the selected cross points is decided. Then even with plural AND arrays 181-183, the input line drive circuit 22 is used in common. Thus, the number of AND arrays is regarded as one in the operation at program except for the operation of switch circuits 211-213.
申请公布号 JPS63164615(A) 申请公布日期 1988.07.08
申请号 JP19860308653 申请日期 1986.12.26
申请人 TOSHIBA CORP;TOSHIBA MICRO COMPUT ENG CORP 发明人 SUZUKI HIROAKI;TSUCHIYA IKUO
分类号 H03K19/177;H01L21/82 主分类号 H03K19/177
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