MULTIPLICATION PROCESSOR

摘要

PURPOSE:To obtain a high-speed multiplier which reduces its hardware quantity with a simple constitution by producing a partial product expressed in the digit number with codes from a multiplicand as well as the two digits of a multiplier recoded by the digit number with codes. CONSTITUTION:A multiplier recoding circuit 101 recodes a multiplier into the 4-notation SD number (digit number with 4-notation code. The partial product generating circuits 102 and 103 produce the redundant binary number (binary SD number) from two digits of the generated 4-notation SD number and a multiplicand. A redundant binary addition circuit 104 adds the partial products in a redundant binary system. The two intermediate partial products have the codes different from each other and therefore no carry is produced at all from the addition of these partial products. Thus the circuit constitution is extremely simplified. A redundant binary/binary converting circuit 105 converts the redundant binary number of the product obtained at the final stage into a binary number. Thus the number of elements of a multiplier can be extremely decreased.