发明名称 2-STAGE PRESET COUNTER
摘要 PURPOSE:To eliminate troubles in the assembling and maintenance by counting a clock pulse to be counted, comparing a count at the discriminating timing from a timing pulse with two preset values to discriminate the quantity of value thereby eliminating the need for a decoder circuit and a timing circuit at the output side. CONSTITUTION:Receiving a clock pulse ck to be counted after the count is made 0, a microcomputer 1 discriminates that a timing pulse Pt does not yet reaches an H level, counts the pulse ck, discriminates whether or not the count is an intermediate value between two preset values SET1, SET2 when the pulse Pt rises and generates no output in case of the intermediate value. On the other hand, if the count of the pulse ck exceeds the high preset value although the pulse Pt does not rise yet, an output is given at an output terminal OUT. Even when the count does not reach the lower preset although the pulse Pt does not rise yet, an output is given from the output terminal OUT. Then in any case, the output is cleared while awaiting the trailing of the pulse Pt to make the count zero.
申请公布号 JPS63196119(A) 申请公布日期 1988.08.15
申请号 JP19870028558 申请日期 1987.02.10
申请人 KEYENCE CORP 发明人 FUKUDA MASAHIKO;SAKAEDA REI
分类号 H03K21/00;H03K23/66 主分类号 H03K21/00
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