| 摘要 |
PURPOSE:To halve the transmission delay of a carry by providing a single transfer gate at every two digital circuit blocks. CONSTITUTION:The full adders 1 and 4 are alternately provided and the transfer gates 19 are set into the adders 4 only. Each adder 4 consists of a half adder 5 and a half adder 6. The adder 5 contains an exclusive OR gate 12 and an AND gate 13 like an existing full adder. While the adder 6 contains two exclusive OR gates 15 and 17, AND gates 14 and 18, an OR gate 16, and an NMOS transistor 19 forming a transfer gate. In other words, the gate 19 is provided every two digits although it is conventionally provided every digit. Thus the number of gates 19 is halved.
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