| 摘要 |
PURPOSE:To reduce a write time to a memory cell by selecting a current amplification factor of an information storage transistor (TR) and a read/write TR smaller than the amplification factor of surrounding TRs. CONSTITUTION:In bipolar memory cell having information storage npn TRs Q1, Q3, read/write npn TRs Q2, Q4 and pnp TRs Q5, Q6 as loads, the current amplification factor beta npn (h) of the information storage TRs Q1, Q3 and the current amplification factor beta npn (R/W) of read/write TRs Q2, Q4 are selected smaller than that of surrounding TRs. Since the emitter/base interval is increased, the throughout of the emitter over the base is reduced, the release of latch is facilitated and write processing is quickened.
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