发明名称 INTER-FRAME CODING SYSTEM
摘要 PURPOSE:To contrive to make the scale of hardware of a movement detector itself small by providing a binarizing circuit binarizing respectively each picture element of both pattern blocks given to the movement detector. CONSTITUTION:The binarizing circuits 5, 6 binarizing each picture element of both pattern blocks inputted to the movement detector 4 are provided in addition to a quantizer 1, a frame memory 2, a variable delay device 3 and the detector 4. An 8-bit picture element data (picture element data of present pattern or a preceding pattern block) is inputted as shown in figure (a) to the binarizing circuits 5, 6, where bit values of Laplacian filter are multiplied with each picture element. Then the result of multiplication is compared with a threshold value for binarizing and it is discriminated as '1' when the result is larger than the threshold value and discriminated as '0' when smaller. This means that the binary edge detection is applied to the pattern. Thus, all picture element data of the pattern block are calculated to generate a binary-coded pattern block and the result is sent to the movement detector 4.
申请公布号 JPS6427380(A) 申请公布日期 1989.01.30
申请号 JP19870183851 申请日期 1987.07.23
申请人 FUJITSU LTD 发明人 KOSUGI YASUHIRO;MATSUDA KIICHI;SAKAI KIYOSHI;HOTTA YASUHIRO;TSUDA TOSHITAKA
分类号 H04N19/423;H04N19/503;H04N19/51;H04N19/543;H04N19/80 主分类号 H04N19/423
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