| 摘要 |
<p>A high speed and extended bit length microprocessor based computer system includes a memory array (5) which is segmented to be addressable by words but shares a common data bus multiple words in size. The computer system further includes a logic circuit (26) for selectively generating and time-synchronizing wait state signals for the microprocessor. The logic circuit (26) is responsive to a memory access request by the microprocessor. The memory access request is considered in conjunction with the previous microprocessor accessing information to determine whether the same segment of the memory array (5) is to be addressed during the next memory array access cycle. If a segment coincidence is detected, a wait cycle is initiated to delay accessing of the memory array. The wait cycle may be a single microprocessor clock cycle or multiples of such time interval. The circuit finds use in a computer system having a microprocessor with a cycle rate faster than the memory array access repetition rate, and which uses software of diverse data word length.</p> |
