| 摘要 |
PURPOSE:To reduce the number of circuit elements, by comparing a plurality of reference signals with a detected signal through time sharing. CONSTITUTION:Upon provision of a reference signal SG1 or SG2, a read-out signal generating circuit 2 outputs a read-out signal 102 with clock timing of a time sharing control signal 101. Consequently, a preset value generating circuit 3 provides a preset data to a write bus line 10. Thereafter, data on the writing bus line is decreased one by one with the clock timing of the time sharing control signal 101, and When the data on the write-in bus line 10 reaches to a predetermined value, an error signal gate 7 opens. If a phase detection signal PG1 or PG2 is provided during this interval, an error signal is written in an error signal memory 9 with the clock timing of an immediately following time sharing control signal 101. |
