| 摘要 |
PURPOSE:To obtain an accurate phase difference signal by retarding a reset signal of an AND gate generating a reset signal through one or two consecutive DFFs or more to operate a DFF pair stably. CONSTITUTION:When twin delayed flip-flops(DFFs) 2, 3 are both at logical 1 with signals f3, Fc incoming, an AND gate 5 outputs this state. The output signal is retarded through DFFs 10, 11 operated at a high frequency f0 into a reset pulse, then the reset pulse is generated with a delay of at least one period of the frequency f0 after the twin DFFs 2, 3 goes to '1'. Thus, the level of the twin DFFs reaching logical 1 with a delay has a firm width and no failure in resetting is caused. In this case, affirmative and negative outputs are ANDed by AND gates 12, 13 to obtain a lead/lag phase difference. Thus, the phase comparator with complete operation and high speed response without steady-state error is obtained. |
