| 摘要 |
PURPOSE:To simplify constitution, to cause a processing speed to be high and to suit for an IC by replacing division with subtraction to utilize a column shift for encoding operation and causing the constitution of an arithmetic part to a pipe line processing. CONSTITUTION:In a first subtracting circuit 50, the subtraction between data to column-shift differential data DATA in a low order only by a bit number BITS and the original differential data DATA is executed and a subtracted result is obtained by a first selector 50. This result is supplied to a second subtracting means 71 in the first step of a first arithmetic means 70 and in the first arithmetic means 70, the division is executed in a way which is completely same as a first encoding method. Accordingly, when an output Q of this first arithmetic means 70 is arranged successively from the first step, the result of the division of a sixth expression can be obtained in a form to be packed to a high order. In a second arithmetic means 90, this divided result under the third decimal place is rounded off and clip is executed. Thus, the constitution is simplified and the processing speed is improved. Then, the IC can be suited. |
