发明名称 BUS LOAD SYSTEM
摘要 PURPOSE:To make the supply of many input/output control devices unnecessary by acquiring a bus using right and controlling bus action at a high rate by one bus load device. CONSTITUTION:A central processing unit, a main memory 30 and an input/ output device such as a minimum disk control device 20 necessary for testing the action are supplied and they are connected to a bus 100 together with a bus load device 10. A transfer rate is calculated from the highest allowable bus 100 use frequency and the bite width of the bus 100 and it is set from a console 12 through a diagnostic processor 11 into a transfer rate setting register 1. Here, when a test program is run, a bus activation request circuit 2 generates the activation request of the bus 100 in a timing fit for the transfer rate set in the transfer rate setting register 1, a bus control circuit 3 acquires the right to use the bus 100, the so-called dummy bus action control is executed. Thus, the supply of the many input/output devices becomes unnecessary.
申请公布号 JPH01187658(A) 申请公布日期 1989.07.27
申请号 JP19880011915 申请日期 1988.01.21
申请人 NEC CORP 发明人 ISHIKAWA ATSUSHI
分类号 G06F11/22;G06F13/00 主分类号 G06F11/22
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