发明名称 |
SEMICONDUCTOR GATE ARRAY DEVICE |
摘要 |
PURPOSE:To obtain large delay time without decreasing the number of standard gate cells by connecting delay means between at least two input/output circuits out of a plurality of the I/O circuits so as to input or output signals into each standard gate cell. CONSTITUTION:A delay circuit is constructed between an output buffer circuit 13 and a Schmit input buffer circuit 14 which act as surplus I/O circuits out of a plurality of I/O circuits which are disposed at peripheral parts of a gate cell group on a substrate. These electrode parts 15 and 16 are connected each other by a conduction part 17 for connection and one side of the electrode 16 is connected to a device pin 18 which exhibits only a position schematically. Protective resistor 21 is inserted in series into the side of an output end of the output buffer circuit 13. A CR delay circuit is composed of the above protective resistor 21 and a capacitor C which is formed between the electrode pad 16 and the substrate. |
申请公布号 |
JPH029150(A) |
申请公布日期 |
1990.01.12 |
申请号 |
JP19880160521 |
申请日期 |
1988.06.28 |
申请人 |
SHARP CORP |
发明人 |
MATSUMURA HIROYUKI |
分类号 |
H01L21/822;H01L21/82;H01L27/04;H01L27/118;H03K5/13;H03K5/133;H03K19/173 |
主分类号 |
H01L21/822 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|