发明名称 APPARATUS AND METHOD FOR DIGITAL PHASE SYNCHRONIZATION
摘要 <p>PURPOSE: To synchronize input data with a local clock without using a phase- locked loop by judging whether or not the effective log clock is at a current clock position from the bit pattern in a window. CONSTITUTION: The signal from a local oscillator 9 is sent to a delay element string 11 and changed into plural delayed clock groups. Those clocks are sent to a transition detector 13 through a register to detect transition in a waveform, which is sent to a selecting device 14. A filter 15 of the selecting device 14 removes all bits except one active bit and this single active bit is regarded as the current clock position. When the single active bit enters the selection window SW, the clock position corresponding to the current output is selected and synchronized as the local clock. If the active state bit is not in the bit pattern in the selection window SW, a next bit is checked.</p>
申请公布号 JPH0255440(A) 申请公布日期 1990.02.23
申请号 JP19890123038 申请日期 1989.05.18
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 KAARIN GAROU MERUROOZE;JIYOU DEBUIDO ROOZE
分类号 H03L7/06;H03L7/081;H04L7/00;H04L7/033 主分类号 H03L7/06
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