SEMICONDUCTOR MEMORY DEVICE HAVING NIBBLE MODE FUNCTION

摘要

The semiconductor memory device comprises memory cell arrays divided into two gps. of first and second cell blocks (CB1,CB2) each provided with data bus lines. Sense amplifier (SB0-SB3) are provided separately to each of the data bus lines. A column decoder (CD') is connected between bit lines provided in the memory cell array and the corresponding data has lines based on address signals and gate signals in a selection state. A device switches betwen sense amplifiers belonging to the first cell block and sense amplifiers belonging to the second cell block and connects these sense amplifiers to output buffers.