| 摘要 |
The processing system includes a host CPU and a number of external memories. Each external memory is formed of a smart memory having a large memory capacity, a linear address arrangement and an arithmetic and logical function. The host CPU and each smart memory are coupled by a common intermediate language. The number of accesses between the host CPU and each smart memory having a large memory capacity decreases, that is, an access gap is reduced. The host CPU and the smart memories can be coupled to one another by the common intermediate language in a specific manner, even when internal languages used in the smart memories are different from each other.
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