| 摘要 |
I/O lines on a CMOS circuit are precharged to preferred voltage levels in order to avoid latch up. The precharging is achieved by using N channel transistors to provide a precharge which is at a threshold voltage (VT) below bias voltage VCC, or (VCC-VT). This results in a lower forward bias when VCC bumps down after the I/O lines are floated. By lowering the precharge voltage by a level corresponding to a threshold voltage (VT), the allowed range of power supply voltage bumping is increased by this amount. This eliminmates the destructive effect of a negative bump of VBE, which would have presented a diode forward bias condition. Instead, the power supply may bump to (VBE+VT).
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