| 摘要 |
A memory uses address transition detection to reduce power consumption of the output amplification stage. The output amplification stage, which drives an output driver, has a series of stages which are disabled except when there is an address transition. When there is an address transition all of the stages are quickly enabled except the last stage. The last stage has its output clamped to an invalid state when the other stages are first enabled and then is enabled a predetermined time after the other stages are enabled. The output of the last stage is sensed by a detector. After the last stage has been enabled and is providing valid data, the detector detects that the output of the last stage is valid, and the series of stages are all disabled. The output driver latches the data and provides an output. The output stage is thus disabled and thus not wasting power except during the portion of a cycle when there is actual need for amplification. The stage at which valid data is detected, which is the last stage, is clamped and disabled at the beginning of the cycle to ensure that the detector does not detect, as being valid, data that is invalid.
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