| 摘要 |
PURPOSE:To generate pattern data without increasing capacity by a circuit receiving a plurality of bits in parallel to perform logical operation at every corresponding control bit and a circuit receiving the output thereof in parallel to store the same as pattern data. CONSTITUTION:A bit reversal control circuit 12 and a pattern data memory circuit 11 storing the output data thereof are provided. The data of the circuit 11 is applied to the circuit 12 as a control bit to allow the pattern data generated one before to act as a reversal condition and the data accessed presently is reversed to generate the next pattern data. By this method, the pattern data is determined by the combination of the data in the previous address and the data in the present address and different pattern data are generated even when the same address is accessed and, even when the kinds of memory data of a memory are scarce, pattern data varying by a number possible in the combination of data can be formed. |
