发明名称 CONTROLLABLE DELAY LOGIC CIRCUIT
摘要 <p>PURPOSE:To match the variance of transmission delay time owing to IC manufacture variance to a desired value by connecting a serial circuit consisting of a control resistance and a control diode to a pull up resistance in parallel. CONSTITUTION:The serial circuit consisting of load circuits RL1 and RL11 and current control elements D1 and D2 which are connected in parallel and in which a conductive state can be controlled from an external part is provided and the variable control of continuous transmission delay time tpd is attained by a control signal voltage V6 given to a control terminal C.</p>
申请公布号 JPH03148914(A) 申请公布日期 1991.06.25
申请号 JP19890286567 申请日期 1989.11.02
申请人 FUJITSU LTD 发明人 EMORI SHINJI;TAMAMURA MASAYA
分类号 H03K5/13;H03K19/086 主分类号 H03K5/13
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