CIRCUIT ARRANGEMENT FOR DISTRIBUTING ON-CHIP GENERATED TEST PATTERNS WITH AT LEAST ONE SCAN PATH

摘要

A circuit arrangement for distributing on-chip generated test patterns with at least one scan path is described. With this arrangement, dependencies between individual test patterns are eliminated with the aid of networks of exclusive-OR gates (EO) between different scan path stages (Z). With this arrangement it is possible to apply individual, very productive test patterns specifically to certain circuit components (K) and to eliminate linear dependencies between test patterns in a targeted manner. Significant Figure 1