| 摘要 |
PURPOSE:To enable circuit design which does not required fast time-division arithmetic much, namely, is reasonable by interposing plural data selecting circuits in each specific delay stage in a delay circuit loop. CONSTITUTION:A cyclic register means 17 holds plural samples of musical sound signal sample data of each channel and is equipped with a series of delay circuits 31, 33, 36 - 38, 48, and 51 which hold respective sample data while delaying them in order. Those delay circuits 31, 33, 36 - 38, 48, and 51 are connected endlessly to constitute a circulation loop and plural data selecting circuits 30, 32, and 39 are interposed in every specific delay means. Then the data selecting circuits 30, 32, and 39 perform selective control over whether the input of new musical signal sample data to the delay circuit loop from a musical sound signal generating means or the circulation of data in the delay circuit loop is performed. Consequently, fast time-division arithmetic is not required to maintain a necessary sampling frequency. |
