发明名称 SUBTRACTION PROCESSOR APPLIED WITH LOGICAL CODE 0-CONVERSION
摘要 PURPOSE:To carry out the binary subtraction at high speed by performing the subtraction conversion in circuit constitution where the logical arithmetic of an exclusive OR is mainly carried out without using a special circuit structure needed for borrowing a digit when the subtraction is performed by an electronic computer. CONSTITUTION:A 4-digit subtracted register 3 which can store the result of subtraction stores a binary number 1000, and a 4-digit subtraction register 4 stores a binary number 0010 with the same position secured among those digits. Then each code of the higher rank digits starting at a digit 6 of the register 3 having the same position as a digit 5 of a code 1 of the register 4 is converted into a code of an exclusive OR secured with the code 1(7) up to a digit 8 where the code is equal to '0'. Thus the subtraction conversion is attained and a subtraction conversion code (9)0110 of the register 3 which recorded the result of the subtraction conversion is the result of subtraction. As a result, the binary subtraction is carried out at high speed.
申请公布号 JPH04113419(A) 申请公布日期 1992.04.14
申请号 JP19900234115 申请日期 1990.09.04
申请人 TAKANO AKIRA 发明人 TAKANO AKIRA
分类号 G06F7/50 主分类号 G06F7/50
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