| 摘要 |
The description consists in disclosing an information-processing system architecture composed of an assembly of standard processors connected in parallel across DHWs (=BUSES), in the form of a two-dimensional matrix. The complete operational system can be composed of one or more elementary blocks (1024 blocks at most), each having at least 64 processors connected in the form of an 8 x 8 two-dimensional grid. The fundamental concept underlying this system is that of embracing within one hardware assembly the following three factors: - the use of conventional processors (industry standards) in large number, - the construction of rxr matrix-like connections (the example of a block with 64 processors is given by r = 8), - the use of parallel DHWs (data highways) as opposed to straightforward serial links. <IMAGE>
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