| 摘要 |
<p>The invention relates to a CMOS circuit protected against latch-up. A peak limiter (2) in parallel with the internal circuitry (1) of the CMOS circuit raises the external current (I'1) for triggering latch-up in the event of an overvoltage in the supply. In one embodiment, the parallel peak limiter is intrinsically protected from electrostatic discharges. In another embodiment, the peak limiter is protected by electrostatic discharge protection associated with a series resistor allowing the triggering of the electrostatic discharge protection and limiting the current passing through the peak limiter. <IMAGE></p> |
