| 摘要 |
PURPOSE:To improve the debugging efficiency at the time of program development of an application system by writing trace data in a trace memory till an instruction operation code fetch cycle (signal M1) and displaying inverse assembling even at the time of qualify trace. CONSTITUTION:An AND circuit 20 outputs a trace enable set signal 23 by the rise of an RAW strobe signal 4 because a qualify condition success signal 8 is active and a signal M1 6 is inputted. An AND circuit 21 does not output a trace enable reset signal 24 because the qualify condition signal 8 is inverted and masked. When receiving the trace enable set signal 23, an SR flip flop circuit 16 makes a trace enable signal 27 active. At this time, AND between this signal 27 and an R/W strobe signal 4 is operated by an AND circuit 22 to output a trace memory write signal 25, and trace data is written in a trace memory 12. |
