| 摘要 |
<p>PURPOSE:To reduce cross skew by making input and output characteristics equal each other to a clock signal for each circuit block of the semiconductor integrated circuit, connecting input terminals in common, and providing combined buffers composed of the prescribed number of unit clock buffers arranged adjacently one and another. CONSTITUTION:The input and output characteristics are made equal each other, the input terminals are connected in common, and plural combined buffers 1 are provided while being composed of unit clock buffers (B1-Bm) arranged adjacently one and another. Since the unit clock buffers B1-Bm having the mutually equal input and output characteristics in respect to the clock signal are adjacently arranged on a chip area, propagating time from the clock signal source of this LSI can be made equal among the respective unit clock buffers, and time for signal propagation to a clock signal load can be easily made equal one and another.</p> |
