| 摘要 |
1,089,098. Semi-conductor devices. MOTOROLA Inc. Nov. 16, 1965 [Dec. 14, 1964], No. 48625/65. Heading H1K. A method of forming isolated regions embedded in a substrate comprises masking a semiconductor starting wafer 10, epitaxially depositing a region 14 of semi-conductor material, applying a layer 30 of insulating material, and a substrate 32 over the region and the surrounding surface of the wafer and then removing the starting wafer, Figs. 2A to 2D. The starting wafer 10 may be removed by etching and the substrate 32 may be flattened by etching or polishing. Transistors are formed by selective diffusion into the deposited regions 14. The masking layer may be silicon dioxide which is treated by heating in HC1 vapour to prevent deposition of semi-conductor material on it during the subsequent process. Insulating layer 30 may also be of silicon dioxide and substrate 32 may be polycrystalline silicon deposited by reduction of SiHCl 3 . The top layer of the deposited epitaxial region may be heavily doped so that in the final structure a conductive layer underlies the isolated region to reduce the collector series resistance of the transistor, Figs. 3A and 3B (not shown). Two regions of opposite conductivity types may be produced by epitaxially depositing a region of one type and covering with a layer of silicon dioxide, Fig. 4A (not shown), etching a new window, epitaxially depositing a region of the opposite type, covering with an oxide layer and depositing a polycrystalline substrate, Fig. 4B (not shown), and then removing the starting wafer, Fig. 4C (not shown). PNP and NPN transistors are formed in the two regions by appropriate diffusions Fig. 5 (not shown). During the epitaxial deposition of the silicon, HBr or HCI may be introduced into the gas stream to control the profile of the deposited regions. The epitaxial regions may be doped by adding the hydrides or halides of phosphorus, arsenic, antimony or boron to the gas stream. Apparatus suitable for the deposition of the various layers on a plurality of wafers is illustrated diagrammatically in Fig. 1 (not shown).
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