| 摘要 |
<p>PURPOSE: To provide an inter power voltage generation circuit which can prevent the drop of the operation speed of an inner element on a chip by means of the temporary voltage drop of inner power voltage which is caused when the potential of external power voltage is lower than that of reference voltage. CONSTITUTION: When the potential of external power voltage ext. Vcc is lower than that of reference voltage Vref, a signal G4 becomes a logic 'high' state in accordance with the output of a low reference voltage generation circuit 400 and transmission gates P3 and N4 are turned off. Then, a pull down transistor N6 is turned on. A driver 90 is interrupted from the output signal of a comparator 20 and it becomes a complete conductive state. Thus, external power voltage ect. Vcc is directly supplied in the chip. Even if inner power voltage int. Vcc temporarily drops, stable external power voltage ext. Vcc is supplied in the chip. Thus, the drop of operation speed can effectively be prevented.</p> |
