发明名称 |
COMPARING COUNTER CONTENTS FOR TIMING CRITICAL APPLICATIONS |
摘要 |
An electrical circuit for comparing contents of counter circuits. The electrical circuit comprises a first counter circuit and a second counter circuit electrically connected to a flip-flop circuit through a logic circuit and OR gates connected to the flip flop circuit. The first counter circuit is for receiving a first enable signal and generating a first output signal. The second counter circuit is for receiving a second enable signal and generating a second output signal. The first enable signal and the second enable signal are for comparing the first output signal to the second output signal. The flip-flop circuit is for generating a first status signal defining a first relationship between the first output signal and the second output signal. The logic circuit is for generating a second status signal defining a second relationship between the first output signal and the second output signal.
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申请公布号 |
US2008258879(A1) |
申请公布日期 |
2008.10.23 |
申请号 |
US20080052771 |
申请日期 |
2008.03.21 |
申请人 |
AMBILKAR SHRIDHAR N;KURUP GIRISH G |
发明人 |
AMBILKAR SHRIDHAR N.;KURUP GIRISH G. |
分类号 |
G05B1/00;G06F7/02 |
主分类号 |
G05B1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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