| 摘要 |
<p>A stacked SONOS memory is provided to enhance storage density of memory while using alleviated critical dimension using a stacked finFET SONOS memory. An IC(Integrated Circuit) includes first and second SONOS memory cells. The second SONOS(Silicon Oxide Nitride Oxide Semiconductor) memory cell is stacked on the first SONOS memory cell. The first and second SONOS memory cells include respectively first and second finFET(Field Effect Transistor) SONOS memory cells. The IC further includes word lines(146) for forming gates of the first and second SONOS memory cells. The first and second SONOS memory cells having NAND memories are formed on an SOI(Silicon On Insulator) wafer.</p> |
