发明名称 |
HARDWARE ACCELERATION FOR A SOFTWARE TRANSACTIONAL MEMORY SYSTEM |
摘要 |
A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardware support, such as a transaction field/transaction bits, are provided to determine if an access is the first access to a shared memory line during a pendancy of a transaction. Additionally, in an aggressive operational mode version numbers representing versions of elements stored in shared memory lines are not stored and validated upon commitment to save on validation costs. Moreover, even in a cautious mode, that stores version numbers to enable validation, validation costs may not be incurred, if eviction of accessed shared memory lines do not occur during execution of the transaction. |
申请公布号 |
WO2007092422(A3) |
申请公布日期 |
2008.10.23 |
申请号 |
WO2007US03112 |
申请日期 |
2007.02.06 |
申请人 |
INTEL CORPORATION;SAHA, BRATIN;ADL-TABATABAI, ALI-REZA;JACOBSON, QUINN |
发明人 |
SAHA, BRATIN;ADL-TABATABAI, ALI-REZA;JACOBSON, QUINN |
分类号 |
G06F9/46 |
主分类号 |
G06F9/46 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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