发明名称 METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH MASKLESS SUPERLATTICE DEPOSITION FOLLOWING STI FORMATION AND RELATED STRUCTURES
摘要 A semiconductor device may include a semiconductor substrate having a surface, a shallow trench isolation (STI) region in the semiconductor substrate and extending above the surface thereof, and a superlattice layer adjacent the surface of the semiconductor substrate and comprising a plurality of stacked groups of layers. More particularly, each group of layers of the superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, at least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer. The semiconductor device may further include a lateral spacer between the superlattice layer and the STI region and which may include a lower non-monocrystalline semiconductor superlattice portion and an upper dielectric portion.
申请公布号 US2008258134(A1) 申请公布日期 2008.10.23
申请号 US20080102305 申请日期 2008.04.14
申请人 MEARS TECHNOLOGIES, INC. 发明人 MEARS ROBERT J.;RAO KALIPATNAM VIVEK
分类号 H01L29/15;H01L21/762 主分类号 H01L29/15
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