发明名称 |
Method of controlled low-k via etch for Cu interconnections |
摘要 |
An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.
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申请公布号 |
US2008258308(A1) |
申请公布日期 |
2008.10.23 |
申请号 |
US20070788969 |
申请日期 |
2007.04.23 |
申请人 |
LIU WUPING;WIDODO JOHNNY;TANG TECK JUNG;LI JING HUI;NG HAN WAH;CLEVENGER LARRY A;WENDT HERMANN |
发明人 |
LIU WUPING;WIDODO JOHNNY;TANG TECK JUNG;LI JING HUI;NG HAN WAH;CLEVENGER LARRY A.;WENDT HERMANN |
分类号 |
H01L21/4763;H01L21/76;H01L29/40 |
主分类号 |
H01L21/4763 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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