| 摘要 |
<p>A variable delay circuit (1) comprises a multistage delay circuit (20) in which delay elements (D1-Dn) are series connected; a selecting part (21) that selects one of delay signals of different delay amounts obtained by causing a reference clock to pass through one or more of the delay elements (D1-Dn); a determining part (23) that determines, at determination timings synchronous with the reference clock, the signal logics of the sequentially selected ones of the delay signals; and a change point detecting part (24) that detects at least two delay elements (Dm,Dk) exhibiting changes in the logic of the reference clock at the determination timings. The difference (k-m) between a number of delay elements through which a clock signal passes to the detected element (Dm) and a number of delay elements through which the clock signal passes to the detected element (Dk) is used as the number of delay elements with which a desired delay time occurs.</p> |
