| 摘要 |
In order to generate a parity of output data from a priority encoder without increasing processing time or making the circuitry complex, the present invention a first level generator (4) having a plurality of first component circuits (10-1 to 10-8) arranged in parallel, into each of which one of a plurality of sets of a specific number of bits of the binary data in sequence from the most significant bit is input and each of which generates and outputs a first signal for parity generation of bit data of the specific number of bits and a second signal representing whether or not the entire bit data of the specific number of bits is "0s" or "1s"; and a second level generator (5) generating the parity of the binary data based on the first signal and the second signal from each of said first component circuits (10-1 to 10-8) of said first level generator (4).
|
