| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL circuit capable of automatically setting output horizontal synchronizing signals same as the frequency of inputted horizontal synchronizing signals even in the case that it is not required to perform conversion from interlaced scanning to successive scanning. SOLUTION: In this PLL circuit constituted of a phase comparator 1, a loop filter 2, a voltage controlled oscillator 3, a variable frequency divider 41, a 2 frequency divider 5 and a switch 7 for switching the output of the variable frequency divider 41 and the 2 frequency divider 5 and sending it to the phase comparator 1, by the output of a horizontal synchronizing signal frequency detection circuit constituted of a counter 8, a reference clock generation circuit 9, an average value calculation circuit 11 and a comparator 10, the variable frequency divider 41 and the switch 7 are controlled. |
