| 摘要 |
<p>The modulator has a counter (11) to output a counter signal (M) based on a preset clock signal (CLK), and clocked with a crystal oscillator. A comparator (10) compares a digital input signal (D) with an actual counter reading (Z) based on a preset assignment table. The comparator resets the counter when the signal (D) corresponds to the reading assigned by the table so that a preset signal value e.g. counter's most significant bit (MSB), of the signal (M) is phase modulated based on the input signal. The counter, the comparator and a transmission stage are integrated in a common logic module. An independent claim is also included for a method for producing a phase modulated digital signal.</p> |
