| 摘要 |
An electronic circuit (10) comprises at least two transistors (T12, T14) coupled in parallel. The first transistor (T12) is biased with a first gate-source voltage and a first drain-source voltage. The second transistor (T14) is biased with a second gate-source voltage and a second drain-source voltage. The first gate-source voltage and the second gate-source voltage are offset from each other by a gate-source voltage offset and the first drain-source voltage and the second drain-source voltage are offset from each other by a drain-source voltage offset. These bias conditions result in the transistors (T12, T14) operating in different regions so that the second and third-order nonlinearities of the transistors (T12, T14) substantially cancel each other out simultaneously.
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