Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations

摘要

An embodiment may comprise memory with a memory array, a resistor coupled to a reference voltage, on die termination circuitry coupled with the resistor, and an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive a calibration command to stop use of the input and the memory array and calibrate the on die termination circuitry with the resistor coupled to the reference voltage. Other embodiments are disclosed herein.