Capacitance trimming circuit of semiconductor device having vertically stacked capacitor layers and operation method thereof

摘要

A capacitance trimming circuit of a semiconductor device may include a plurality of capacitor layers and/or a plurality of fuses. The plurality of capacitor layers may be vertically stacked. The plurality of fuses may be arranged to correspond to the plurality of capacitor layers, and/or the plurality of fuses may be configured to select corresponding ones of the plurality of capacitor layers for controlling a capacitance of the plurality of capacitor layers.