发明名称
摘要 <p>A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.</p>
申请公布号 JP2008535247(A) 申请公布日期 2008.08.28
申请号 JP20080504064 申请日期 2006.02.27
申请人 发明人
分类号 H01L21/3205 主分类号 H01L21/3205
代理机构 代理人
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